The present invention relates to testing of integrated circuits with an automated test equipment.
Integrated Circuits (IC) generally need to be tested to assure proper operation. This—in particular—is required during IC development and manufacturing. In the latter case, the ICs are usually tested before final application. During test, the IC, as a device under test (DUT), is exposed to various types of stimulus signals, and its responses are measured, processed and usually compared to an expected response of a good device. Automated test equipment (ATE) usually performs these tasks according to a device-specific test program.
ATEs based various architectures have been applied for testing integrated circuits. For testing complex high speed circuits, ATEs with decentralized resources based on a per-pin architecture are known, wherein during test, each pin of a multiple of the pins of the DUT that are relevant for a test, is connected to one of a multiple the ATE pin electronic. Such an ATE further comprises central resources, in particular for controlling the sequence and timing of applied test stimulus vectors. The per-pin architecture generally enables high performance and scalability. Examples for ATEs with per-pin architecture are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A-886214, EP-A-882991, U.S. Pat. No. 5,499,248, U.S. Pat. No. 5,453,995.
Processor speed of integrated circuits or systems integrated on a chip is continuously increasing. For testing those circuits or systems, it is necessary to provide automatic test equipment that is able to cope with the speed demands. However, raising data rates of current ATEs is not possible without a fundamental architectural redesign.